Wishbone Bus

The wishbone bus is an open-specification for a hardware protocol for connecting two hardware devices. These could be CPUs, RAMs, GPUs, USB controllers, whatever. It was created out of necessity by the open-source-hardware community, since the existing bus protocol standards are all locked down with patents, copyright, and trademarks.

It seems to me that a bus interface should “just work”. You should be able to plug any 2 compliant devices into it and they can now talk to eachother. But wishbone puts a major roadblock in the way right away:

Devices can have varying data widths: 8bit, 16bit, 32bit, or 64bit. You can’t just connect a 8bit wishbone device to a 32bit wishbone device, you need to do some conversion logic. There’s no built-in standard for adaptively using fewer bits.

Wishbone tries to solve this by adding the ability for devices to support a lower “granularity” than this data width. So maybe a device supports a 32bit data bus, but you can write to it 8bits at a time. The way this is implemented poses a problem though. It works by supplying a series of “select” signals which decide which of the sections of the data bus should be accepted. For instance, a device could do a 32-bit write, but specify that only bytes 0 and 2 should be accepted by the receiver, bytes 1 and 3 should be discarded and not overwrite anything.

So the problem arises in certain cases such as this one: A device supporting a 64-bit data bus (Device X) attempts to write to a 32-bit device (Device Y). Device X has a granularity of 16bits, and specifies that the second and fourth 16bit sections are to be accepted by Device Y. But Device Y only supports a granularity of 32 bits. So it can’t accept this transfer.

The designer will notice that Device X provides select lines, and Device Y doesn’t accept select lines, and will hopefully not connect these two devices directly. But even the circuitry to convert this transfer from what Device X wants to what Device Y can support is very tricky.

(I’m not really doing a good job of explaining the problem. TL;DR is: This open spec bus was is overly permissive, and it results in more work on the part of system designers to make use of it, since most of the time two devices that “support the wishbone bus” can’t simply be connected together, you have to do all this conversion stuff… between devices that (ostensibly) talk the same protocol!)

(Also I realize that other busses get around this problem by simply specifying everything. “Use 32-bit values always”, “Use 32-bit values and always support 8-bit granularity”, etc. But I’d argue that that’s an improvement.)

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