I’ve been looking at various open-source RISC-V cores to hook up to the 2D sprite renderer I’ve been working on, and it looks like Rocket Chip is the way to go, since it’s so highly-configurable. That’s perfect for me, because game system cores have always been highly custom.
Let’s see what it takes to build some RTL on a stock Ubuntu 18.04 LTS install:
# Install dependencies echo "deb https://dl.bintray.com/sbt/debian /" | \ sudo tee -a /etc/apt/sources.list.d/sbt.list sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 \ --recv 642AC823 sudo apt-get update sudo apt-get install git autoconf automake autotools-dev \ curl libmpc-dev libmpfr-dev libgmp-dev libusb-1.0-0-dev \ gawk build-essential bison flex texinfo gperf libtool \ patchutils bc zlib1g-dev device-tree-compiler pkg-config \ libexpat-dev g++ flex bison python default-jdk sbt git clone git@github.com:chipsalliance/rocket-chip cd rocket-chip git submodule update --init git clone https://github.com/freechipsproject/rocket-tools cd rocket-tools git submodule update --init --recursive export RISCV=`pwd` export MAKEFLAGS="$MAKEFLAGS -j2" ./build.sh ./build-rv32ima.sh cd ../vsim # According to the README, we now need to run "make". make # You will likely get an "IO Error While decoding" error. # Just run "make" a second time. # This will still appear to fail due to # "vcs: command not found". VCS is a RTL simulator # like Icarus Verilog, but I think it's a paid product. # This leads me to believe that this "make" command # might be optional. make # Now (finally) build the verilog output! make verilog CONFIG=DefaultFPGAConfig # Let's see the output... ls -laSh generated-src
Okay, if all goes well, in generated-src you should have the conveniently-named “freechips.rocketchip.system.DefaultFPGAConfig.v”
At this point I think I’ve added enough value to this post to publish it.
Next steps:
- Delete the TestHarness module from the file (“freechips.rocketchip.system.DefaultFPGAConfig.v”, which I’ve renamed “freechips.rocketchip.system.DefaultFPGAConfig_TestHarness_removed.v”)
- Add my own SystemVerilog testbench file, which will instantiate “ExampleRocketSystem” from the file (“Rocket” is the actual top-level module, but that only exposes a TileLink interface, and might be missing some default configuration).
- Copy some necessary verilog files into the generated-src directory (just because it seems more convenient to me, you can leave them where they are.
- Run it through Icarus Verilog
let me dump a BASH snippet here:
# Let's try to simulate things in icarus verilog cd generated-src # Let's copy some other verilog files we need into this subdirectory cp -r ../../src/main/resources/vsrc/ ./ iverilog '-Wall' '-g2012' \ freechips.rocketchip.system.DefaultFPGAConfig_TestHarness_removed.v \ freechips.rocketchip.system.DefaultFPGAConfig.behav_srams.v \ ./vsrc/AsyncResetReg.v \ ./vsrc/EICG_wrapper.v \ ./vsrc/plusarg_reader.v \ testbench.sv \ && vvp a.out
TODO: Finish up the test bench and get it to run some assembly code (I’ll probably have to add the “SimAXIMem” from TestHarness…)
Here’s my testbench.sv file:
`default_nettype none
`timescale 1ns/1ps
module main_testbench;
reg clock = 0;
reg reset = 0;
wire dut_debug_clockeddmi_dmi_req_ready;
// wire dut_debug_clockeddmi_dmi_req_valid;
reg dut_debug_clockeddmi_dmi_req_valid = 0;
wire [6:0] dut_debug_clockeddmi_dmi_req_bits_addr;
wire [31:0] dut_debug_clockeddmi_dmi_req_bits_data;
wire [1:0] dut_debug_clockeddmi_dmi_req_bits_op;
// wire dut_debug_clockeddmi_dmi_resp_ready;
reg dut_debug_clockeddmi_dmi_resp_ready = 0;
wire dut_debug_clockeddmi_dmi_resp_valid;
wire [31:0] dut_debug_clockeddmi_dmi_resp_bits_data;
wire [1:0] dut_debug_clockeddmi_dmi_resp_bits_resp;
wire dut_debug_clockeddmi_dmiClock;
wire dut_debug_clockeddmi_dmiReset;
wire dut_debug_ndreset;
wire dut_debug_dmactive;
// wire [1:0] dut_interrupts;
reg [1:0] dut_interrupts = 0;
// wire dut_mem_axi4_0_aw_ready;
reg dut_mem_axi4_0_aw_ready = 1;
wire dut_mem_axi4_0_aw_valid;
wire [3:0] dut_mem_axi4_0_aw_bits_id;
wire [31:0] dut_mem_axi4_0_aw_bits_addr;
wire [7:0] dut_mem_axi4_0_aw_bits_len;
wire [2:0] dut_mem_axi4_0_aw_bits_size;
wire [1:0] dut_mem_axi4_0_aw_bits_burst;
wire dut_mem_axi4_0_aw_bits_lock;
wire [3:0] dut_mem_axi4_0_aw_bits_cache;
wire [2:0] dut_mem_axi4_0_aw_bits_prot;
wire [3:0] dut_mem_axi4_0_aw_bits_qos;
wire dut_mem_axi4_0_w_ready;
wire dut_mem_axi4_0_w_valid;
wire [63:0] dut_mem_axi4_0_w_bits_data;
wire [7:0] dut_mem_axi4_0_w_bits_strb;
wire dut_mem_axi4_0_w_bits_last;
wire dut_mem_axi4_0_b_ready;
wire dut_mem_axi4_0_b_valid;
wire [3:0] dut_mem_axi4_0_b_bits_id;
wire [1:0] dut_mem_axi4_0_b_bits_resp;
wire dut_mem_axi4_0_ar_ready;
wire dut_mem_axi4_0_ar_valid;
wire [3:0] dut_mem_axi4_0_ar_bits_id;
wire [31:0] dut_mem_axi4_0_ar_bits_addr;
wire [7:0] dut_mem_axi4_0_ar_bits_len;
wire [2:0] dut_mem_axi4_0_ar_bits_size;
wire [1:0] dut_mem_axi4_0_ar_bits_burst;
wire dut_mem_axi4_0_ar_bits_lock;
wire [3:0] dut_mem_axi4_0_ar_bits_cache;
wire [2:0] dut_mem_axi4_0_ar_bits_prot;
wire [3:0] dut_mem_axi4_0_ar_bits_qos;
wire dut_mem_axi4_0_r_ready;
wire dut_mem_axi4_0_r_valid;
wire [3:0] dut_mem_axi4_0_r_bits_id;
wire [63:0] dut_mem_axi4_0_r_bits_data;
wire [1:0] dut_mem_axi4_0_r_bits_resp;
wire dut_mem_axi4_0_r_bits_last;
wire dut_mmio_axi4_0_aw_ready;
wire dut_mmio_axi4_0_aw_valid;
wire [3:0] dut_mmio_axi4_0_aw_bits_id;
wire [30:0] dut_mmio_axi4_0_aw_bits_addr;
wire [7:0] dut_mmio_axi4_0_aw_bits_len;
wire [2:0] dut_mmio_axi4_0_aw_bits_size;
wire [1:0] dut_mmio_axi4_0_aw_bits_burst;
wire dut_mmio_axi4_0_aw_bits_lock;
wire [3:0] dut_mmio_axi4_0_aw_bits_cache;
wire [2:0] dut_mmio_axi4_0_aw_bits_prot;
wire [3:0] dut_mmio_axi4_0_aw_bits_qos;
wire dut_mmio_axi4_0_w_ready;
wire dut_mmio_axi4_0_w_valid;
wire [63:0] dut_mmio_axi4_0_w_bits_data;
wire [7:0] dut_mmio_axi4_0_w_bits_strb;
wire dut_mmio_axi4_0_w_bits_last;
wire dut_mmio_axi4_0_b_ready;
wire dut_mmio_axi4_0_b_valid;
wire [3:0] dut_mmio_axi4_0_b_bits_id;
wire [1:0] dut_mmio_axi4_0_b_bits_resp;
wire dut_mmio_axi4_0_ar_ready;
wire dut_mmio_axi4_0_ar_valid;
wire [3:0] dut_mmio_axi4_0_ar_bits_id;
wire [30:0] dut_mmio_axi4_0_ar_bits_addr;
wire [7:0] dut_mmio_axi4_0_ar_bits_len;
wire [2:0] dut_mmio_axi4_0_ar_bits_size;
wire [1:0] dut_mmio_axi4_0_ar_bits_burst;
wire dut_mmio_axi4_0_ar_bits_lock;
wire [3:0] dut_mmio_axi4_0_ar_bits_cache;
wire [2:0] dut_mmio_axi4_0_ar_bits_prot;
wire [3:0] dut_mmio_axi4_0_ar_bits_qos;
wire dut_mmio_axi4_0_r_ready;
wire dut_mmio_axi4_0_r_valid;
wire [3:0] dut_mmio_axi4_0_r_bits_id;
wire [63:0] dut_mmio_axi4_0_r_bits_data;
wire [1:0] dut_mmio_axi4_0_r_bits_resp;
wire dut_mmio_axi4_0_r_bits_last;
wire dut_l2_frontend_bus_axi4_0_aw_ready;
wire dut_l2_frontend_bus_axi4_0_aw_valid;
wire [7:0] dut_l2_frontend_bus_axi4_0_aw_bits_id;
wire [31:0] dut_l2_frontend_bus_axi4_0_aw_bits_addr;
wire [7:0] dut_l2_frontend_bus_axi4_0_aw_bits_len;
wire [2:0] dut_l2_frontend_bus_axi4_0_aw_bits_size;
wire [1:0] dut_l2_frontend_bus_axi4_0_aw_bits_burst;
wire dut_l2_frontend_bus_axi4_0_aw_bits_lock;
wire [3:0] dut_l2_frontend_bus_axi4_0_aw_bits_cache;
wire [2:0] dut_l2_frontend_bus_axi4_0_aw_bits_prot;
wire [3:0] dut_l2_frontend_bus_axi4_0_aw_bits_qos;
wire dut_l2_frontend_bus_axi4_0_w_ready;
wire dut_l2_frontend_bus_axi4_0_w_valid;
wire [63:0] dut_l2_frontend_bus_axi4_0_w_bits_data;
wire [7:0] dut_l2_frontend_bus_axi4_0_w_bits_strb;
wire dut_l2_frontend_bus_axi4_0_w_bits_last;
wire dut_l2_frontend_bus_axi4_0_b_ready;
wire dut_l2_frontend_bus_axi4_0_b_valid;
wire [7:0] dut_l2_frontend_bus_axi4_0_b_bits_id;
wire [1:0] dut_l2_frontend_bus_axi4_0_b_bits_resp;
wire dut_l2_frontend_bus_axi4_0_ar_ready;
wire dut_l2_frontend_bus_axi4_0_ar_valid;
wire [7:0] dut_l2_frontend_bus_axi4_0_ar_bits_id;
wire [31:0] dut_l2_frontend_bus_axi4_0_ar_bits_addr;
wire [7:0] dut_l2_frontend_bus_axi4_0_ar_bits_len;
wire [2:0] dut_l2_frontend_bus_axi4_0_ar_bits_size;
wire [1:0] dut_l2_frontend_bus_axi4_0_ar_bits_burst;
wire dut_l2_frontend_bus_axi4_0_ar_bits_lock;
wire [3:0] dut_l2_frontend_bus_axi4_0_ar_bits_cache;
wire [2:0] dut_l2_frontend_bus_axi4_0_ar_bits_prot;
wire [3:0] dut_l2_frontend_bus_axi4_0_ar_bits_qos;
wire dut_l2_frontend_bus_axi4_0_r_ready;
wire dut_l2_frontend_bus_axi4_0_r_valid;
wire [7:0] dut_l2_frontend_bus_axi4_0_r_bits_id;
wire [63:0] dut_l2_frontend_bus_axi4_0_r_bits_data;
wire [1:0] dut_l2_frontend_bus_axi4_0_r_bits_resp;
wire dut_l2_frontend_bus_axi4_0_r_bits_last;
wire mem_clock;
wire mem_reset;
wire mem_io_axi4_0_aw_ready;
wire mem_io_axi4_0_aw_valid;
wire [3:0] mem_io_axi4_0_aw_bits_id;
wire [27:0] mem_io_axi4_0_aw_bits_addr;
wire [7:0] mem_io_axi4_0_aw_bits_len;
wire [2:0] mem_io_axi4_0_aw_bits_size;
wire [1:0] mem_io_axi4_0_aw_bits_burst;
wire mem_io_axi4_0_w_ready;
wire mem_io_axi4_0_w_valid;
wire [63:0] mem_io_axi4_0_w_bits_data;
wire [7:0] mem_io_axi4_0_w_bits_strb;
wire mem_io_axi4_0_w_bits_last;
wire mem_io_axi4_0_b_ready;
wire mem_io_axi4_0_b_valid;
wire [3:0] mem_io_axi4_0_b_bits_id;
wire [1:0] mem_io_axi4_0_b_bits_resp;
wire mem_io_axi4_0_ar_ready;
wire mem_io_axi4_0_ar_valid;
wire [3:0] mem_io_axi4_0_ar_bits_id;
wire [27:0] mem_io_axi4_0_ar_bits_addr;
wire [7:0] mem_io_axi4_0_ar_bits_len;
wire [2:0] mem_io_axi4_0_ar_bits_size;
wire [1:0] mem_io_axi4_0_ar_bits_burst;
wire mem_io_axi4_0_r_ready;
wire mem_io_axi4_0_r_valid;
wire [3:0] mem_io_axi4_0_r_bits_id;
wire [63:0] mem_io_axi4_0_r_bits_data;
wire [1:0] mem_io_axi4_0_r_bits_resp;
wire mem_io_axi4_0_r_bits_last;
wire mmio_mem_clock;
wire mmio_mem_reset;
wire mmio_mem_io_axi4_0_aw_ready;
wire mmio_mem_io_axi4_0_aw_valid;
wire [3:0] mmio_mem_io_axi4_0_aw_bits_id;
wire [11:0] mmio_mem_io_axi4_0_aw_bits_addr;
wire [7:0] mmio_mem_io_axi4_0_aw_bits_len;
wire [2:0] mmio_mem_io_axi4_0_aw_bits_size;
wire [1:0] mmio_mem_io_axi4_0_aw_bits_burst;
wire mmio_mem_io_axi4_0_w_ready;
wire mmio_mem_io_axi4_0_w_valid;
wire [63:0] mmio_mem_io_axi4_0_w_bits_data;
wire [7:0] mmio_mem_io_axi4_0_w_bits_strb;
wire mmio_mem_io_axi4_0_w_bits_last;
wire mmio_mem_io_axi4_0_b_ready;
wire mmio_mem_io_axi4_0_b_valid;
wire [3:0] mmio_mem_io_axi4_0_b_bits_id;
wire [1:0] mmio_mem_io_axi4_0_b_bits_resp;
wire mmio_mem_io_axi4_0_ar_ready;
wire mmio_mem_io_axi4_0_ar_valid;
wire [3:0] mmio_mem_io_axi4_0_ar_bits_id;
wire [11:0] mmio_mem_io_axi4_0_ar_bits_addr;
wire [7:0] mmio_mem_io_axi4_0_ar_bits_len;
wire [2:0] mmio_mem_io_axi4_0_ar_bits_size;
wire [1:0] mmio_mem_io_axi4_0_ar_bits_burst;
wire mmio_mem_io_axi4_0_r_ready;
wire mmio_mem_io_axi4_0_r_valid;
wire [3:0] mmio_mem_io_axi4_0_r_bits_id;
wire [63:0] mmio_mem_io_axi4_0_r_bits_data;
wire [1:0] mmio_mem_io_axi4_0_r_bits_resp;
wire mmio_mem_io_axi4_0_r_bits_last;
wire SimDTM_clk;
wire SimDTM_reset;
wire SimDTM_debug_req_ready;
wire SimDTM_debug_req_valid;
wire [6:0] SimDTM_debug_req_bits_addr;
wire [31:0] SimDTM_debug_req_bits_data;
wire [1:0] SimDTM_debug_req_bits_op;
wire SimDTM_debug_resp_ready;
wire SimDTM_debug_resp_valid;
wire [31:0] SimDTM_debug_resp_bits_data;
wire [1:0] SimDTM_debug_resp_bits_resp;
wire [31:0] SimDTM_exit;
wire _T_8;
wire [30:0] _GEN_0;
wire [31:0] _T_9;
wire _T_11;
ExampleRocketSystem dut (
.clock(clock),
.reset(reset),
.debug_clockeddmi_dmi_req_ready(dut_debug_clockeddmi_dmi_req_ready),
.debug_clockeddmi_dmi_req_valid(dut_debug_clockeddmi_dmi_req_valid),
.debug_clockeddmi_dmi_req_bits_addr(dut_debug_clockeddmi_dmi_req_bits_addr),
.debug_clockeddmi_dmi_req_bits_data(dut_debug_clockeddmi_dmi_req_bits_data),
.debug_clockeddmi_dmi_req_bits_op(dut_debug_clockeddmi_dmi_req_bits_op),
.debug_clockeddmi_dmi_resp_ready(dut_debug_clockeddmi_dmi_resp_ready),
.debug_clockeddmi_dmi_resp_valid(dut_debug_clockeddmi_dmi_resp_valid),
.debug_clockeddmi_dmi_resp_bits_data(dut_debug_clockeddmi_dmi_resp_bits_data),
.debug_clockeddmi_dmi_resp_bits_resp(dut_debug_clockeddmi_dmi_resp_bits_resp),
.debug_clockeddmi_dmiClock(clock),
.debug_clockeddmi_dmiReset(reset),
.debug_ndreset(dut_debug_ndreset),
.debug_dmactive(dut_debug_dmactive),
.interrupts(dut_interrupts),
.mem_axi4_0_aw_ready(dut_mem_axi4_0_aw_ready),
.mem_axi4_0_aw_valid(dut_mem_axi4_0_aw_valid),
.mem_axi4_0_aw_bits_id(dut_mem_axi4_0_aw_bits_id),
.mem_axi4_0_aw_bits_addr(dut_mem_axi4_0_aw_bits_addr),
.mem_axi4_0_aw_bits_len(dut_mem_axi4_0_aw_bits_len),
.mem_axi4_0_aw_bits_size(dut_mem_axi4_0_aw_bits_size),
.mem_axi4_0_aw_bits_burst(dut_mem_axi4_0_aw_bits_burst),
.mem_axi4_0_aw_bits_lock(dut_mem_axi4_0_aw_bits_lock),
.mem_axi4_0_aw_bits_cache(dut_mem_axi4_0_aw_bits_cache),
.mem_axi4_0_aw_bits_prot(dut_mem_axi4_0_aw_bits_prot),
.mem_axi4_0_aw_bits_qos(dut_mem_axi4_0_aw_bits_qos),
.mem_axi4_0_w_ready(dut_mem_axi4_0_w_ready),
.mem_axi4_0_w_valid(dut_mem_axi4_0_w_valid),
.mem_axi4_0_w_bits_data(dut_mem_axi4_0_w_bits_data),
.mem_axi4_0_w_bits_strb(dut_mem_axi4_0_w_bits_strb),
.mem_axi4_0_w_bits_last(dut_mem_axi4_0_w_bits_last),
.mem_axi4_0_b_ready(dut_mem_axi4_0_b_ready),
.mem_axi4_0_b_valid(dut_mem_axi4_0_b_valid),
.mem_axi4_0_b_bits_id(dut_mem_axi4_0_b_bits_id),
.mem_axi4_0_b_bits_resp(dut_mem_axi4_0_b_bits_resp),
.mem_axi4_0_ar_ready(dut_mem_axi4_0_ar_ready),
.mem_axi4_0_ar_valid(dut_mem_axi4_0_ar_valid),
.mem_axi4_0_ar_bits_id(dut_mem_axi4_0_ar_bits_id),
.mem_axi4_0_ar_bits_addr(dut_mem_axi4_0_ar_bits_addr),
.mem_axi4_0_ar_bits_len(dut_mem_axi4_0_ar_bits_len),
.mem_axi4_0_ar_bits_size(dut_mem_axi4_0_ar_bits_size),
.mem_axi4_0_ar_bits_burst(dut_mem_axi4_0_ar_bits_burst),
.mem_axi4_0_ar_bits_lock(dut_mem_axi4_0_ar_bits_lock),
.mem_axi4_0_ar_bits_cache(dut_mem_axi4_0_ar_bits_cache),
.mem_axi4_0_ar_bits_prot(dut_mem_axi4_0_ar_bits_prot),
.mem_axi4_0_ar_bits_qos(dut_mem_axi4_0_ar_bits_qos),
.mem_axi4_0_r_ready(dut_mem_axi4_0_r_ready),
.mem_axi4_0_r_valid(dut_mem_axi4_0_r_valid),
.mem_axi4_0_r_bits_id(dut_mem_axi4_0_r_bits_id),
.mem_axi4_0_r_bits_data(dut_mem_axi4_0_r_bits_data),
.mem_axi4_0_r_bits_resp(dut_mem_axi4_0_r_bits_resp),
.mem_axi4_0_r_bits_last(dut_mem_axi4_0_r_bits_last),
.mmio_axi4_0_aw_ready(dut_mmio_axi4_0_aw_ready),
.mmio_axi4_0_aw_valid(dut_mmio_axi4_0_aw_valid),
.mmio_axi4_0_aw_bits_id(dut_mmio_axi4_0_aw_bits_id),
.mmio_axi4_0_aw_bits_addr(dut_mmio_axi4_0_aw_bits_addr),
.mmio_axi4_0_aw_bits_len(dut_mmio_axi4_0_aw_bits_len),
.mmio_axi4_0_aw_bits_size(dut_mmio_axi4_0_aw_bits_size),
.mmio_axi4_0_aw_bits_burst(dut_mmio_axi4_0_aw_bits_burst),
.mmio_axi4_0_aw_bits_lock(dut_mmio_axi4_0_aw_bits_lock),
.mmio_axi4_0_aw_bits_cache(dut_mmio_axi4_0_aw_bits_cache),
.mmio_axi4_0_aw_bits_prot(dut_mmio_axi4_0_aw_bits_prot),
.mmio_axi4_0_aw_bits_qos(dut_mmio_axi4_0_aw_bits_qos),
.mmio_axi4_0_w_ready(dut_mmio_axi4_0_w_ready),
.mmio_axi4_0_w_valid(dut_mmio_axi4_0_w_valid),
.mmio_axi4_0_w_bits_data(dut_mmio_axi4_0_w_bits_data),
.mmio_axi4_0_w_bits_strb(dut_mmio_axi4_0_w_bits_strb),
.mmio_axi4_0_w_bits_last(dut_mmio_axi4_0_w_bits_last),
.mmio_axi4_0_b_ready(dut_mmio_axi4_0_b_ready),
.mmio_axi4_0_b_valid(dut_mmio_axi4_0_b_valid),
.mmio_axi4_0_b_bits_id(dut_mmio_axi4_0_b_bits_id),
.mmio_axi4_0_b_bits_resp(dut_mmio_axi4_0_b_bits_resp),
.mmio_axi4_0_ar_ready(dut_mmio_axi4_0_ar_ready),
.mmio_axi4_0_ar_valid(dut_mmio_axi4_0_ar_valid),
.mmio_axi4_0_ar_bits_id(dut_mmio_axi4_0_ar_bits_id),
.mmio_axi4_0_ar_bits_addr(dut_mmio_axi4_0_ar_bits_addr),
.mmio_axi4_0_ar_bits_len(dut_mmio_axi4_0_ar_bits_len),
.mmio_axi4_0_ar_bits_size(dut_mmio_axi4_0_ar_bits_size),
.mmio_axi4_0_ar_bits_burst(dut_mmio_axi4_0_ar_bits_burst),
.mmio_axi4_0_ar_bits_lock(dut_mmio_axi4_0_ar_bits_lock),
.mmio_axi4_0_ar_bits_cache(dut_mmio_axi4_0_ar_bits_cache),
.mmio_axi4_0_ar_bits_prot(dut_mmio_axi4_0_ar_bits_prot),
.mmio_axi4_0_ar_bits_qos(dut_mmio_axi4_0_ar_bits_qos),
.mmio_axi4_0_r_ready(dut_mmio_axi4_0_r_ready),
.mmio_axi4_0_r_valid(dut_mmio_axi4_0_r_valid),
.mmio_axi4_0_r_bits_id(dut_mmio_axi4_0_r_bits_id),
.mmio_axi4_0_r_bits_data(dut_mmio_axi4_0_r_bits_data),
.mmio_axi4_0_r_bits_resp(dut_mmio_axi4_0_r_bits_resp),
.mmio_axi4_0_r_bits_last(dut_mmio_axi4_0_r_bits_last),
.l2_frontend_bus_axi4_0_aw_ready(dut_l2_frontend_bus_axi4_0_aw_ready),
.l2_frontend_bus_axi4_0_aw_valid(dut_l2_frontend_bus_axi4_0_aw_valid),
.l2_frontend_bus_axi4_0_aw_bits_id(dut_l2_frontend_bus_axi4_0_aw_bits_id),
.l2_frontend_bus_axi4_0_aw_bits_addr(dut_l2_frontend_bus_axi4_0_aw_bits_addr),
.l2_frontend_bus_axi4_0_aw_bits_len(dut_l2_frontend_bus_axi4_0_aw_bits_len),
.l2_frontend_bus_axi4_0_aw_bits_size(dut_l2_frontend_bus_axi4_0_aw_bits_size),
.l2_frontend_bus_axi4_0_aw_bits_burst(dut_l2_frontend_bus_axi4_0_aw_bits_burst),
.l2_frontend_bus_axi4_0_aw_bits_lock(dut_l2_frontend_bus_axi4_0_aw_bits_lock),
.l2_frontend_bus_axi4_0_aw_bits_cache(dut_l2_frontend_bus_axi4_0_aw_bits_cache),
.l2_frontend_bus_axi4_0_aw_bits_prot(dut_l2_frontend_bus_axi4_0_aw_bits_prot),
.l2_frontend_bus_axi4_0_aw_bits_qos(dut_l2_frontend_bus_axi4_0_aw_bits_qos),
.l2_frontend_bus_axi4_0_w_ready(dut_l2_frontend_bus_axi4_0_w_ready),
.l2_frontend_bus_axi4_0_w_valid(dut_l2_frontend_bus_axi4_0_w_valid),
.l2_frontend_bus_axi4_0_w_bits_data(dut_l2_frontend_bus_axi4_0_w_bits_data),
.l2_frontend_bus_axi4_0_w_bits_strb(dut_l2_frontend_bus_axi4_0_w_bits_strb),
.l2_frontend_bus_axi4_0_w_bits_last(dut_l2_frontend_bus_axi4_0_w_bits_last),
.l2_frontend_bus_axi4_0_b_ready(dut_l2_frontend_bus_axi4_0_b_ready),
.l2_frontend_bus_axi4_0_b_valid(dut_l2_frontend_bus_axi4_0_b_valid),
.l2_frontend_bus_axi4_0_b_bits_id(dut_l2_frontend_bus_axi4_0_b_bits_id),
.l2_frontend_bus_axi4_0_b_bits_resp(dut_l2_frontend_bus_axi4_0_b_bits_resp),
.l2_frontend_bus_axi4_0_ar_ready(dut_l2_frontend_bus_axi4_0_ar_ready),
.l2_frontend_bus_axi4_0_ar_valid(dut_l2_frontend_bus_axi4_0_ar_valid),
.l2_frontend_bus_axi4_0_ar_bits_id(dut_l2_frontend_bus_axi4_0_ar_bits_id),
.l2_frontend_bus_axi4_0_ar_bits_addr(dut_l2_frontend_bus_axi4_0_ar_bits_addr),
.l2_frontend_bus_axi4_0_ar_bits_len(dut_l2_frontend_bus_axi4_0_ar_bits_len),
.l2_frontend_bus_axi4_0_ar_bits_size(dut_l2_frontend_bus_axi4_0_ar_bits_size),
.l2_frontend_bus_axi4_0_ar_bits_burst(dut_l2_frontend_bus_axi4_0_ar_bits_burst),
.l2_frontend_bus_axi4_0_ar_bits_lock(dut_l2_frontend_bus_axi4_0_ar_bits_lock),
.l2_frontend_bus_axi4_0_ar_bits_cache(dut_l2_frontend_bus_axi4_0_ar_bits_cache),
.l2_frontend_bus_axi4_0_ar_bits_prot(dut_l2_frontend_bus_axi4_0_ar_bits_prot),
.l2_frontend_bus_axi4_0_ar_bits_qos(dut_l2_frontend_bus_axi4_0_ar_bits_qos),
.l2_frontend_bus_axi4_0_r_ready(dut_l2_frontend_bus_axi4_0_r_ready),
.l2_frontend_bus_axi4_0_r_valid(dut_l2_frontend_bus_axi4_0_r_valid),
.l2_frontend_bus_axi4_0_r_bits_id(dut_l2_frontend_bus_axi4_0_r_bits_id),
.l2_frontend_bus_axi4_0_r_bits_data(dut_l2_frontend_bus_axi4_0_r_bits_data),
.l2_frontend_bus_axi4_0_r_bits_resp(dut_l2_frontend_bus_axi4_0_r_bits_resp),
.l2_frontend_bus_axi4_0_r_bits_last(dut_l2_frontend_bus_axi4_0_r_bits_last)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
always #4 clock = ~clock;
initial begin
reset = 1; #16 reset = 0;
#500
$finish();
end
endmodule
When I run this, it doesn’t actually do anything, and by that I mean, not a single signal changes state after reset, presumably it’s waiting for some AXI handshaking to take place, or maybe I’m holding it in some reset state somehow. I’ll have to look at TestHarness more closely…
